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| author | Alistair Francis | 2019-06-25 00:11:49 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-06-27 11:47:06 +0200 |
| commit | 0ac24d56c5e7d32423ea78ac58a06b444d1df04d (patch) | |
| tree | f92aa46bc262c12a463f5896afa8e885502956e5 /python | |
| parent | riscv: sifive_u: Update the plic hart config to support multicore (diff) | |
| download | qemu-0ac24d56c5e7d32423ea78ac58a06b444d1df04d.tar.gz qemu-0ac24d56c5e7d32423ea78ac58a06b444d1df04d.tar.xz qemu-0ac24d56c5e7d32423ea78ac58a06b444d1df04d.zip | |
hw/riscv: Split out the boot functions
Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions