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| author | Bin Meng | 2020-10-28 06:30:08 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-11-03 16:17:23 +0100 |
| commit | 27c22b2de08f71500df581563cc9d22638a14b4d (patch) | |
| tree | 97076925e1db576b9b4c7fde3ca413964d79f3cc /python | |
| parent | hw/riscv: microchip_pfsoc: Connect the SYSREG module (diff) | |
| download | qemu-27c22b2de08f71500df581563cc9d22638a14b4d.tar.gz qemu-27c22b2de08f71500df581563cc9d22638a14b4d.tar.xz qemu-27c22b2de08f71500df581563cc9d22638a14b4d.zip | |
hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.
[1] See the config_copy() calls in various places in ddr_setup() in
the HSS source codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions