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| author | Frederic Barrat | 2022-04-11 14:59:00 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza | 2022-04-20 23:00:30 +0200 |
| commit | 4e610064dbcb2425de03cfd541a6393280c463c9 (patch) | |
| tree | 2d421354e5efbf8c9c4f6ef2e0386913886786fb /python | |
| parent | ppc/pnv: Remove LSI on the PCIE host bridge (diff) | |
| download | qemu-4e610064dbcb2425de03cfd541a6393280c463c9.tar.gz qemu-4e610064dbcb2425de03cfd541a6393280c463c9.tar.xz qemu-4e610064dbcb2425de03cfd541a6393280c463c9.zip | |
target/ppc: Add two missing register callbacks on POWER10
This patch adds tcg accessors for 2 SPRs which were missing on P10:
- the TBU40 register is used to write the upper 40 bits of the
timebase register. It is used by kvm to update the timebase when
entering/exiting the guest on P9 and above. The missing definition was
causing erratic decrementer interrupts in a pseries/kvm guest running
in a powernv10/tcg host, typically resulting in hangs.
- the missing DPDES SPR was found through code inspection. It exists
unchanged on P10.
Both existed on previous versions of the processor and a bit of git
archaeology hints that they were added while the P10 model was already
being worked on so they may have simply fallen through the cracks.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220411125900.352028-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions