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| author | Bin Meng | 2019-09-06 18:19:58 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:46 +0200 |
| commit | 56449d20e937e807e4fc35fa3e5a38f7636e7046 (patch) | |
| tree | 43aba52df5fbc31c9135873e04506163ddb773e8 /python | |
| parent | riscv: sifive_u: Remove the unnecessary include of prci header (diff) | |
| download | qemu-56449d20e937e807e4fc35fa3e5a38f7636e7046.tar.gz qemu-56449d20e937e807e4fc35fa3e5a38f7636e7046.tar.xz qemu-56449d20e937e807e4fc35fa3e5a38f7636e7046.zip | |
riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions
