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| author | Cédric Le Goater | 2019-03-07 23:35:44 +0100 |
|---|---|---|
| committer | David Gibson | 2019-03-12 04:33:04 +0100 |
| commit | 5dad902ce09877a97a6f32e5f6c75b4f8506bd73 (patch) | |
| tree | e17c6171757a39c2072a4b3909b9c77dbf5150ac /python | |
| parent | ppc/pnv: extend XSCOM core support for POWER9 (diff) | |
| download | qemu-5dad902ce09877a97a6f32e5f6c75b4f8506bd73.tar.gz qemu-5dad902ce09877a97a6f32e5f6c75b4f8506bd73.tar.xz qemu-5dad902ce09877a97a6f32e5f6c75b4f8506bd73.zip | |
ppc/pnv: POWER9 XSCOM quad support
The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.
Provide a basic Quad model to fake the settings done by the firmware
on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special
BAR setting for the TIMA area of XIVE because it resides on the same
address on all chips.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-12-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions