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| author | Joel Sing | 2019-06-24 20:08:38 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-06-26 07:37:04 +0200 |
| commit | c13b169f1a3dd158d6c75727cdc388f95988db39 (patch) | |
| tree | d23c2fd911b809c36128fa626e36076a31253826 /python | |
| parent | RISC-V: Add support for the Zicsr extension (diff) | |
| download | qemu-c13b169f1a3dd158d6c75727cdc388f95988db39.tar.gz qemu-c13b169f1a3dd158d6c75727cdc388f95988db39.tar.xz qemu-c13b169f1a3dd158d6c75727cdc388f95988db39.zip | |
RISC-V: Clear load reservations on context switch and SC
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.
Signed-off-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions