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| author | Georg Kotheimer | 2021-03-11 11:30:36 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-03-23 02:54:40 +0100 |
| commit | db9ab38b81058b41e5f469165067feea46762eee (patch) | |
| tree | 5c516e847992578958b66c421d001c68a114393d /python | |
| parent | target/riscv: Make VSTIP and VSEIP read-only in hip (diff) | |
| download | qemu-db9ab38b81058b41e5f469165067feea46762eee.tar.gz qemu-db9ab38b81058b41e5f469165067feea46762eee.tar.xz qemu-db9ab38b81058b41e5f469165067feea46762eee.zip | |
target/riscv: Use background registers also for MSTATUS_MPV
The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions