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| author | Peter Maydell | 2018-07-16 18:18:41 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-07-16 18:18:41 +0200 |
| commit | 7995206d057409cff9d4e850bdc8296c8fc21d38 (patch) | |
| tree | 83854b91bf802b76d66beafd7566e27550eec4e9 /qapi | |
| parent | hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq() (diff) | |
| download | qemu-7995206d057409cff9d4e850bdc8296c8fc21d38.tar.gz qemu-7995206d057409cff9d4e850bdc8296c8fc21d38.tar.xz qemu-7995206d057409cff9d4e850bdc8296c8fc21d38.zip | |
hw/intc/arm_gic: Fix handling of GICD_ITARGETSR
The GICD_ITARGETSR implementation still has some 11MPCore behaviour
that we were incorrectly using in our GICv1 and GICv2 implementations
for the case where the interrupt number is less than GIC_INTERNAL.
The desired behaviour here is:
* for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the
CPU doing the read for irqs 29..31
* for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a
number matching the CPU doing the read for all irqs < 32
Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this
is an 11MPCore GIC.
Reported-by: Jan Kiszka <jan.kiszka@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180712154152.32183-3-peter.maydell@linaro.org
Diffstat (limited to 'qapi')
0 files changed, 0 insertions, 0 deletions