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| author | Peter Maydell | 2018-11-06 12:32:14 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-11-06 12:32:14 +0100 |
| commit | 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512 (patch) | |
| tree | b8aef0dbd207a9a7d9cd02b923efa17229ae948e /qdev-monitor.c | |
| parent | target/arm: Set S and PTW in 64-bit PAR format (diff) | |
| download | qemu-23463e0e4aeb2f0a9c60549a2c163f4adc0b8512.tar.gz qemu-23463e0e4aeb2f0a9c60549a2c163f4adc0b8512.tar.xz qemu-23463e0e4aeb2f0a9c60549a2c163f4adc0b8512.zip | |
target/arm: Fix ATS1Hx instructions
ATS1HR and ATS1HW (which allow AArch32 EL2 to do address translations
on the EL2 translation regime) were implemented in commit 14db7fe09a2c8.
However, we got them wrong: these should do stage 1 address translations
as defined for NS-EL2, which is ARMMMUIdx_S1E2. We were incorrectly
making them perform stage 2 translations.
A few years later in commit 1313e2d7e2cd we forgot entirely that
we'd implemented ATS1Hx, and added a comment that ATS1Hx were
"not supported yet". Remove the comment; there is no extra code
needed to handle these operations in do_ats_write(), because
arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2,
which forces 64-bit PAR format.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20181016093703.10637-3-peter.maydell@linaro.org
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'qdev-monitor.c')
0 files changed, 0 insertions, 0 deletions