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author | Max Filippov | 2020-06-30 23:52:25 +0200 |
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committer | Max Filippov | 2020-08-21 21:48:15 +0200 |
commit | e95ef43181b49a401d163729d0d96f304525dfe7 (patch) | |
tree | 17b1eec6333d72b90f255cc3f2ba9c4b86349421 /replication.c | |
parent | tests/tcg/xtensa: fix test execution on ISS (diff) | |
download | qemu-e95ef43181b49a401d163729d0d96f304525dfe7.tar.gz qemu-e95ef43181b49a401d163729d0d96f304525dfe7.tar.xz qemu-e95ef43181b49a401d163729d0d96f304525dfe7.zip |
tests/tcg/xtensa: update test_fp0_arith for DFPU
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the arithmetic tests.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'replication.c')
0 files changed, 0 insertions, 0 deletions