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authorDamien Hedde2020-04-06 15:52:49 +0200
committerPeter Maydell2020-04-30 16:35:41 +0200
commitb636db306e06ee1c267d6e15e3b5bc109252617f (patch)
tree14208dc493429ed2095af75b5c6a8d6a7631ce30 /replication.h
parenthw/misc/zynq_slcr: add clock generation for uarts (diff)
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hw/char/cadence_uart: add clock support
Switch the cadence uart to multi-phase reset and add the reference clock input. The input clock frequency is added to the migration structure. The reference clock controls the baudrate generation. If it disabled, any input characters and events are ignored. If this clock remains unconnected, the uart behaves as before (it default to a 50MHz ref clock). Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200406135251.157596-8-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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