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| author | Yifei Jiang | 2020-10-14 12:17:28 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-10-22 21:00:22 +0200 |
| commit | 33a9a57d2c31ec9ed68858911dc490b5de15f342 (patch) | |
| tree | 8bd77284ba8e8e1ab3e09089040d24f4f25cbc55 /scripts/check_sparse.py | |
| parent | hw/riscv: Load the kernel after the firmware (diff) | |
| download | qemu-33a9a57d2c31ec9ed68858911dc490b5de15f342.tar.gz qemu-33a9a57d2c31ec9ed68858911dc490b5de15f342.tar.xz qemu-33a9a57d2c31ec9ed68858911dc490b5de15f342.zip | |
target/riscv: raise exception to HS-mode at get_physical_address
VS-stage translation at get_physical_address needs to translate pte
address by G-stage translation. But the G-stage translation error
can not be distinguished from VS-stage translation error in
riscv_cpu_tlb_fill. On migration, destination needs to rebuild pte,
and this G-stage translation error must be handled by HS-mode. So
introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could
distinguish and raise it to HS-mode.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201014101728.848-1-jiangyifei@huawei.com
[ Change by AF:
- Clarify the fault_pte_addr shift
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/check_sparse.py')
0 files changed, 0 insertions, 0 deletions