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| author | Idan Horowitz | 2022-04-01 16:35:49 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-04-01 16:35:49 +0200 |
| commit | bcd7a8cf38b7e9769f741419bc56675cbddb42c6 (patch) | |
| tree | f82f8210b4f8b5ccc89712dfef72554d7fa39f00 /scripts/check_sparse.py | |
| parent | target/arm: Check VSTCR.SW when assigning the stage 2 output PA space (diff) | |
| download | qemu-bcd7a8cf38b7e9769f741419bc56675cbddb42c6.tar.gz qemu-bcd7a8cf38b7e9769f741419bc56675cbddb42c6.tar.xz qemu-bcd7a8cf38b7e9769f741419bc56675cbddb42c6.zip | |
target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk
As per the AArch64.SS2InitialTTWState() psuedo-code in the ARMv8 ARM the
initial PA space used for stage 2 table walks is assigned based on the SW
and NSW bits of the VSTCR and VTCR registers.
This was already implemented for the recursive stage 2 page table walks
in S1_ptw_translate(), but was missing for the final stage 2 walk.
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220327093427.1548629-3-idan.horowitz@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/check_sparse.py')
0 files changed, 0 insertions, 0 deletions