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| author | Stefan Hajnoczi | 2022-11-17 17:55:53 +0100 |
|---|---|---|
| committer | Stefan Hajnoczi | 2022-11-21 15:28:43 +0100 |
| commit | c74831a02c818f89d10f5475cd0fb9ba40bfb2a8 (patch) | |
| tree | cb95ede0c6e62a64870ba113d70ecbfa17b6a905 /scripts/check_sparse.py | |
| parent | rtl8139: avoid clobbering tx descriptor bits (diff) | |
| download | qemu-c74831a02c818f89d10f5475cd0fb9ba40bfb2a8.tar.gz qemu-c74831a02c818f89d10f5475cd0fb9ba40bfb2a8.tar.xz qemu-c74831a02c818f89d10f5475cd0fb9ba40bfb2a8.zip | |
rtl8139: keep Tx command mode 0 and 1 separate
There are two Tx Descriptor formats called mode 0 and mode 1. The mode
is determined by the Large Send bit.
CP_TX_IPCS (bit 18) is defined in mode 1 but the code checks the bit
unconditionally. In mode 0 bit 18 is part of the Large Send MSS value.
Explicitly check the Large Send bit to distinguish Tx command modes.
This avoids bugs where modes are confused. Note that I didn't find any
actual bugs aside from needlessly computing the IP checksum when the
Large Send bit is enabled.
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20221117165554.1773409-3-stefanha@redhat.com>
Diffstat (limited to 'scripts/check_sparse.py')
0 files changed, 0 insertions, 0 deletions