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| author | Michael Clark | 2019-03-16 02:20:28 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-03-19 13:14:39 +0100 |
| commit | c124c152428559216c5d083e11a35e51f773c007 (patch) | |
| tree | eab91cd368bdffb76b054e9e8d4f4b6f6fa3b54e /scripts/checkpatch.pl | |
| parent | RISC-V: Allow interrupt controllers to claim interrupts (diff) | |
| download | qemu-c124c152428559216c5d083e11a35e51f773c007.tar.gz qemu-c124c152428559216c5d083e11a35e51f773c007.tar.xz qemu-c124c152428559216c5d083e11a35e51f773c007.zip | |
RISC-V: Remove unnecessary disassembler constraints
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/checkpatch.pl')
0 files changed, 0 insertions, 0 deletions