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| author | Richard Henderson | 2018-10-24 08:50:20 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-24 08:51:37 +0200 |
| commit | f478847f1ee0df9397f561025ab2f687fd923571 (patch) | |
| tree | 44349b20caf1b5efb8b50fa474a4f466758398e5 /scripts/checkpatch.pl | |
| parent | net: cadence_gem: Announce 64bit addressing support (diff) | |
| download | qemu-f478847f1ee0df9397f561025ab2f687fd923571.tar.gz qemu-f478847f1ee0df9397f561025ab2f687fd923571.tar.xz qemu-f478847f1ee0df9397f561025ab2f687fd923571.zip | |
target/arm: Remove writefn from TTBR0_EL3
The EL3 version of this register does not include an ASID,
and so the tlb_flush performed by vmsa_ttbr_write is not needed.
Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20181019015617.22583-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/checkpatch.pl')
0 files changed, 0 insertions, 0 deletions