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| author | Peter Maydell | 2018-01-11 14:25:40 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-01-11 14:25:40 +0100 |
| commit | 0cf09852015e47a5fbb974ff7ac320366afd21ee (patch) | |
| tree | beade5d3d69aca0e4e7e1b29728effc133b693da /scripts/device-crash-test | |
| parent | hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI (diff) | |
| download | qemu-0cf09852015e47a5fbb974ff7ac320366afd21ee.tar.gz qemu-0cf09852015e47a5fbb974ff7ac320366afd21ee.tar.xz qemu-0cf09852015e47a5fbb974ff7ac320366afd21ee.zip | |
hw/intc/arm_gic: reserved register addresses are RAZ/WI
The GICv2 specification says that reserved register addresses
must RAZ/WI; now that we implement external abort handling
for Arm CPUs this means we must return MEMTX_OK rather than
MEMTX_ERROR, to avoid generating a spurious guest data abort.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1513183941-24300-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Diffstat (limited to 'scripts/device-crash-test')
0 files changed, 0 insertions, 0 deletions