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| author | Richard Henderson | 2021-11-17 10:51:29 +0100 |
|---|---|---|
| committer | Richard Henderson | 2021-11-17 10:51:29 +0100 |
| commit | 52cebbfc133fb784644edeae1e5b53aac3b64e5f (patch) | |
| tree | 74b27b822e26a5690a23659fbe1e93d5418bfcc7 /scripts/device-crash-test | |
| parent | Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (diff) | |
| parent | meson.build: Merge riscv32 and riscv64 cpu family (diff) | |
| download | qemu-52cebbfc133fb784644edeae1e5b53aac3b64e5f.tar.gz qemu-52cebbfc133fb784644edeae1e5b53aac3b64e5f.tar.xz qemu-52cebbfc133fb784644edeae1e5b53aac3b64e5f.zip | |
Merge tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu into staging
Sixth RISC-V PR for QEMU 6.2
- Fix build for riscv hosts
- Soft code alphabetically
# gpg: Signature made Wed 17 Nov 2021 10:19:25 AM CET
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
* tag 'pull-riscv-to-apply-20211117-1' of github.com:alistair23/qemu:
meson.build: Merge riscv32 and riscv64 cpu family
target/riscv: machine: Sort the .subsections
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'scripts/device-crash-test')
0 files changed, 0 insertions, 0 deletions