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| author | Peter Maydell | 2019-02-28 11:55:16 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-28 12:03:04 +0100 |
| commit | c0c760afe800b60b48c80ddf3509fec413594778 (patch) | |
| tree | 24803174754f6d04204e3e61921e76c1ec73c6f6 /scripts/git-submodule.sh | |
| parent | target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions (diff) | |
| download | qemu-c0c760afe800b60b48c80ddf3509fec413594778.tar.gz qemu-c0c760afe800b60b48c80ddf3509fec413594778.tar.xz qemu-c0c760afe800b60b48c80ddf3509fec413594778.zip | |
target/arm: Gate "miscellaneous FP" insns by ID register field
There is a set of VFP instructions which we implement in
disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
These were all first introduced in v8 for A-profile, but in
M-profile they appeared in v7M. Gate them on the MVFR2
FPMisc field instead, and rename the function appropriately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
Diffstat (limited to 'scripts/git-submodule.sh')
0 files changed, 0 insertions, 0 deletions