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| author | Richard Henderson | 2019-04-25 19:26:36 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:25 +0200 |
| commit | 4cc16b3b9282e04fab8e84d136540757e82af019 (patch) | |
| tree | a6caaae619e90e0d1bd36105f1fb986847435c53 /scripts/git.orderfile | |
| parent | target/riscv: Add the HGATP register masks (diff) | |
| download | qemu-4cc16b3b9282e04fab8e84d136540757e82af019.tar.gz qemu-4cc16b3b9282e04fab8e84d136540757e82af019.tar.xz qemu-4cc16b3b9282e04fab8e84d136540757e82af019.zip | |
target/riscv: Add checks for several RVC reserved operands
C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved
operands that were not diagnosed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/git.orderfile')
0 files changed, 0 insertions, 0 deletions