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| author | Atish Patra | 2022-08-25 00:16:59 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-09-07 09:19:15 +0200 |
| commit | 892320facd73136b48bb58af3bd742686eb05416 (patch) | |
| tree | 341768428045b8636be354fe309caffcefc9ec63 /scripts/kernel-doc | |
| parent | target/riscv: Simplify counter predicate function (diff) | |
| download | qemu-892320facd73136b48bb58af3bd742686eb05416.tar.gz qemu-892320facd73136b48bb58af3bd742686eb05416.tar.xz qemu-892320facd73136b48bb58af3bd742686eb05416.zip | |
target/riscv: Add few cache related PMU events
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221701.41932-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/kernel-doc')
0 files changed, 0 insertions, 0 deletions