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| author | Alex Zuepke | 2022-04-28 15:27:17 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-05-05 10:36:22 +0200 |
| commit | 99a50d1a67c602126fc2b3a4812d3000eba9bf34 (patch) | |
| tree | d9c884c619ccfdae3c8e38764d50c28591ce894c /scripts/meson-buildoptions.py | |
| parent | target/arm: Add isar_feature_{aa64,any}_ras (diff) | |
| download | qemu-99a50d1a67c602126fc2b3a4812d3000eba9bf34.tar.gz qemu-99a50d1a67c602126fc2b3a4812d3000eba9bf34.tar.xz qemu-99a50d1a67c602126fc2b3a4812d3000eba9bf34.zip | |
target/arm: read access to performance counters from EL0
The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.
Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/meson-buildoptions.py')
0 files changed, 0 insertions, 0 deletions