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| author | Peter Maydell | 2019-05-24 14:42:48 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-06-17 16:13:19 +0200 |
| commit | 0edfcc9ec06fbbcc154cce64748752a5c565a32c (patch) | |
| tree | cbf0438772a74fde51ae90459fdcfbd5416c3ff5 /scripts/modules/module_block.py | |
| parent | hw/intc/arm_gicv3: Fix decoding of ID register range (diff) | |
| download | qemu-0edfcc9ec06fbbcc154cce64748752a5c565a32c.tar.gz qemu-0edfcc9ec06fbbcc154cce64748752a5c565a32c.tar.xz qemu-0edfcc9ec06fbbcc154cce64748752a5c565a32c.zip | |
hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
The GICv3 specification says that the GICD_TYPER.SecurityExtn bit
is RAZ if GICD_CTLR.DS is 1. We were incorrectly making it RAZ
if the security extension is unsupported. "Security extension
unsupported" always implies GICD_CTLR.DS == 1, but the guest can
also set DS on a GIC which does support the security extension.
Fix the condition to correctly check the GICD_CTLR.DS bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190524124248.28394-3-peter.maydell@linaro.org
Diffstat (limited to 'scripts/modules/module_block.py')
0 files changed, 0 insertions, 0 deletions