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| author | Bin Meng | 2019-09-06 18:20:06 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:47 +0200 |
| commit | ecdfe393b69985eb90ac4921287439dc47ed35b4 (patch) | |
| tree | 18e3169109e7b7dde7bea572a48d9335bf9949f9 /scripts/modules/module_block.py | |
| parent | riscv: sifive_u: Set the minimum number of cpus to 2 (diff) | |
| download | qemu-ecdfe393b69985eb90ac4921287439dc47ed35b4.tar.gz qemu-ecdfe393b69985eb90ac4921287439dc47ed35b4.tar.xz qemu-ecdfe393b69985eb90ac4921287439dc47ed35b4.zip | |
riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.
The cpu nodes in the generated DTS have been updated as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/modules/module_block.py')
0 files changed, 0 insertions, 0 deletions