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authorMichael Davidsaver2017-02-28 13:08:18 +0100
committerPeter Maydell2017-02-28 13:08:18 +0100
commit14790f730a9b7da026f5562505d1004f67abebf5 (patch)
tree5ddd2e418ed13befb7572856e229ef64136132d1 /scripts/modules
parentarmv7m: Simpler and faster exception start (diff)
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armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
The VECTCLRACTIVE and VECTRESET bits in the AIRCR are both documented as UNPREDICTABLE if you write a 1 to them when the processor is not halted in Debug state (ie stopped and under the control of an external JTAG debugger). Since we don't implement Debug state or emulated JTAG these bits are always UNPREDICTABLE for us. Instead of logging them as unimplemented we can simply log writes as guest errors and ignore them. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: change extracted from another patch; commit message constructed from scratch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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