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| author | Michael Clark | 2018-03-02 13:31:13 +0100 |
|---|---|---|
| committer | Michael Clark | 2018-03-06 20:30:28 +0100 |
| commit | 5b4beba1246ff163415bde41cd76935012b16823 (patch) | |
| tree | ac3596e00957f860fefdfdf2503aff64ef229f74 /scripts/modules | |
| parent | SiFive RISC-V PLIC Block (diff) | |
| download | qemu-5b4beba1246ff163415bde41cd76935012b16823.tar.gz qemu-5b4beba1246ff163415bde41cd76935012b16823.tar.xz qemu-5b4beba1246ff163415bde41cd76935012b16823.zip | |
RISC-V Spike Machines
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:
- 'spike_v1.9.1'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'scripts/modules')
0 files changed, 0 insertions, 0 deletions