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| author | Peter Maydell | 2017-10-06 17:46:49 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-10-06 17:46:49 +0200 |
| commit | 9901c576f6c02d43206e5faaf6e362ab7ea83246 (patch) | |
| tree | 6404c526e5ac316a996c32d6e703e2cb399957a7 /scripts/modules | |
| parent | target/arm: Add v8M support to exception entry code (diff) | |
| download | qemu-9901c576f6c02d43206e5faaf6e362ab7ea83246.tar.gz qemu-9901c576f6c02d43206e5faaf6e362ab7ea83246.tar.xz qemu-9901c576f6c02d43206e5faaf6e362ab7ea83246.zip | |
nvic: Implement Security Attribution Unit registers
Implement the register interface for the SAU: SAU_CTRL,
SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the
actual behaviour is implemented here; registers just
read back as written.
When the CPU definition for Cortex-M33 is eventually
added, its initfn will set cpu->sau_sregion, in the same
way that we currently set cpu->pmsav7_dregion for the
M3 and M4.
Number of SAU regions is typically a configurable
CPU parameter, but this patch doesn't provide a
QEMU CPU property for it. We can easily add one when
we have a board that requires it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1506092407-26985-14-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'scripts/modules')
0 files changed, 0 insertions, 0 deletions