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| author | Bin Meng | 2019-03-17 09:03:11 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-03-19 13:18:42 +0100 |
| commit | a9ec1c76d57491602b4d3b521f898905825ca848 (patch) | |
| tree | c92ba2a23b71389ac9c5f68db0d60aca5d381396 /scripts/modules | |
| parent | riscv: sifive_uart: Generate TX interrupt (diff) | |
| download | qemu-a9ec1c76d57491602b4d3b521f898905825ca848.tar.gz qemu-a9ec1c76d57491602b4d3b521f898905825ca848.tar.xz qemu-a9ec1c76d57491602b4d3b521f898905825ca848.zip | |
riscv: sifive_u: Correct UART0's IRQ in the device tree
The UART0's interrupt vector is wrongly set to 1 in the device tree.
Use SIFIVE_U_UART0_IRQ instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/modules')
0 files changed, 0 insertions, 0 deletions