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| author | Michael Clark | 2018-03-02 13:31:14 +0100 |
|---|---|---|
| committer | Michael Clark | 2018-03-06 20:30:28 +0100 |
| commit | e6b8552c655aad405e7dc28d84b4a6d5324f1b92 (patch) | |
| tree | 5532b74c8d05909e1579b6cbbf815e1784f42a7a /scripts/modules | |
| parent | SiFive RISC-V UART Device (diff) | |
| download | qemu-e6b8552c655aad405e7dc28d84b4a6d5324f1b92.tar.gz qemu-e6b8552c655aad405e7dc28d84b4a6d5324f1b92.tar.xz qemu-e6b8552c655aad405e7dc28d84b4a6d5324f1b92.zip | |
SiFive RISC-V PRCI Block
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'scripts/modules')
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