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| author | Stefan Markovic | 2018-08-02 16:16:34 +0200 |
|---|---|---|
| committer | Aleksandar Markovic | 2018-08-16 19:18:45 +0200 |
| commit | fa192d4974de3ace960d03803ab9d2f09abd9282 (patch) | |
| tree | 1603e933969b7fc8c7c2893aaf43a7122bb533db /scripts/modules | |
| parent | target/mips: Add CP0 BadInstrX register (diff) | |
| download | qemu-fa192d4974de3ace960d03803ab9d2f09abd9282.tar.gz qemu-fa192d4974de3ace960d03803ab9d2f09abd9282.tar.xz qemu-fa192d4974de3ace960d03803ab9d2f09abd9282.zip | |
target/mips: Implement CP0 Config1.WR bit functionality
Add testing Config1.WR bit into watch exception handling logic.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Diffstat (limited to 'scripts/modules')
0 files changed, 0 insertions, 0 deletions