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| author | Paolo Bonzini | 2013-03-12 13:16:28 +0100 |
|---|---|---|
| committer | Paolo Bonzini | 2014-05-13 13:12:40 +0200 |
| commit | 43175fa96add507afee6c0a83ec9ffe0ca130fc3 (patch) | |
| tree | 3b720e0bcd3c0d806f0276bf8e38f9943bb38ee2 /scripts/qapi-commands.py | |
| parent | target-i386: fix set of registers zeroed on reset (diff) | |
| download | qemu-43175fa96add507afee6c0a83ec9ffe0ca130fc3.tar.gz qemu-43175fa96add507afee6c0a83ec9ffe0ca130fc3.tar.xz qemu-43175fa96add507afee6c0a83ec9ffe0ca130fc3.zip | |
target-i386: preserve FPU and MSR state on INIT
Most MSRs, plus the FPU, MMX, MXCSR, XMM and YMM registers should not
be zeroed on INIT (Table 9-1 in the Intel SDM). Copy them out of
CPUX86State and back in, instead of special casing env->pat.
The relevant fields are already consecutive except PAT and SMBASE.
However:
- KVM and Hyper-V MSRs should be reset because they include memory
locations written by the hypervisor. These MSRs are moved together
at the end of the preserved area.
- SVM state can be moved out of the way since it is written by VMRUN.
Cc: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'scripts/qapi-commands.py')
0 files changed, 0 insertions, 0 deletions