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| author | Jeff Kubascik | 2020-01-17 15:09:31 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-01-17 15:27:16 +0100 |
| commit | 30d544839e278dc76017b9a42990c41e84a34377 (patch) | |
| tree | 6c7c500d2c8dfa76d4805445c70ec7eb981ad601 /scripts/qapi/parser.py | |
| parent | arm/gicv3: update virtual irq state after IAR register read (diff) | |
| download | qemu-30d544839e278dc76017b9a42990c41e84a34377.tar.gz qemu-30d544839e278dc76017b9a42990c41e84a34377.tar.xz qemu-30d544839e278dc76017b9a42990c41e84a34377.zip | |
target/arm: Return correct IL bit in merge_syn_data_abort
The IL bit is set for 32-bit instructions, thus passing false
with the is_16bit parameter to syn_data_abort_with_iss() makes
a syn mask that always has the IL bit set.
Pass is_16bit as true to make the initial syn mask have IL=0,
so that the final IL value comes from or'ing template_syn.
Cc: qemu-stable@nongnu.org
Fixes: aaa1f954d4ca ("target-arm: A64: Create Instruction Syndromes for Data Aborts")
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200117004618.2742-2-richard.henderson@linaro.org
[rth: Extracted this as a self-contained bug fix from a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/qapi/parser.py')
0 files changed, 0 insertions, 0 deletions