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| author | Xi Wang | 2019-01-27 00:02:56 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-02-12 00:56:22 +0100 |
| commit | ff9f31d9a0d45da83f34207b7ccace850cfc465b (patch) | |
| tree | b7534aab035d6dc28eac82d16325b8c6f484db19 /scripts/qemugdb/coroutine.py | |
| parent | MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer (diff) | |
| download | qemu-ff9f31d9a0d45da83f34207b7ccace850cfc465b.tar.gz qemu-ff9f31d9a0d45da83f34207b7ccace850cfc465b.tar.xz qemu-ff9f31d9a0d45da83f34207b7ccace850cfc465b.zip | |
target/riscv: fix counter-enable checks in ctr()
Access to a counter in U-mode is permitted only if the corresponding
bit is set in both mcounteren and scounteren. The current code
ignores mcounteren and checks scounteren only for U-mode access.
Signed-off-by: Xi Wang <xi.wang@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/qemugdb/coroutine.py')
0 files changed, 0 insertions, 0 deletions