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| author | Atish Patra | 2020-07-01 20:39:46 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-07-14 02:25:37 +0200 |
| commit | 43cf723adca9a5e188c664c3b606a585192a599c (patch) | |
| tree | b9e8397567d10b3a4dc41640dec663b52a77be27 /scripts/render_block_graph.py | |
| parent | hw/riscv: virt: Sort the SoC memmap table entries (diff) | |
| download | qemu-43cf723adca9a5e188c664c3b606a585192a599c.tar.gz qemu-43cf723adca9a5e188c664c3b606a585192a599c.tar.xz qemu-43cf723adca9a5e188c664c3b606a585192a599c.zip | |
riscv: Unify Qemu's reset vector code path
Currently, all riscv machines except sifive_u have identical reset vector
code implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.
Move it to common function and let all the machines use the common function.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-2-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/render_block_graph.py')
0 files changed, 0 insertions, 0 deletions