diff options
| author | Sven Schnelle | 2019-03-11 20:15:53 +0100 |
|---|---|---|
| committer | Richard Henderson | 2019-03-12 17:13:43 +0100 |
| commit | 0b49c3398851622ead40c7e1fc3144d3187123fd (patch) | |
| tree | d71178aa06052ae9cbd580353a495da70d574e3b /scripts/switch-timer-api | |
| parent | target/hppa: fix overwriting source reg in addb (diff) | |
| download | qemu-0b49c3398851622ead40c7e1fc3144d3187123fd.tar.gz qemu-0b49c3398851622ead40c7e1fc3144d3187123fd.tar.xz qemu-0b49c3398851622ead40c7e1fc3144d3187123fd.zip | |
target/hppa: fix TLB handling for page 0
Assume the following sequence:
pitlbe r0(sr0,r0)
iitlba r4,(sr0,r0)
ldil L%3000000,r5
iitlbp r5,(sr0,r0)
This will purge the whole TLB and add an entry for page 0. However
the current TLB implementation in helper_iitlba() will store to
the last empty TLB entry, while helper_iitlbp() will write to the
first empty entry. That is because an empty entry will match address
0 in helper_iitlba()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190311191602.25796-3-svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions