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| author | Michael Clark | 2018-04-30 01:06:31 +0200 |
|---|---|---|
| committer | Michael Clark | 2018-05-06 00:39:38 +0200 |
| commit | 1dc34be1c90b2d3006078d9d331e53a849cdecf3 (patch) | |
| tree | 7011d38f076ea00bb3ed9ec2fc711f03d953d1c1 /scripts/switch-timer-api | |
| parent | RISC-V: Include instruction hex in disassembly (diff) | |
| download | qemu-1dc34be1c90b2d3006078d9d331e53a849cdecf3.tar.gz qemu-1dc34be1c90b2d3006078d9d331e53a849cdecf3.tar.xz qemu-1dc34be1c90b2d3006078d9d331e53a849cdecf3.zip | |
RISC-V: Fix missing break statement in disassembler
This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions