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| author | Peter Maydell | 2019-02-01 15:55:43 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-01 15:55:43 +0100 |
| commit | 5aeb36896600ff92aee1083ed17e80f069befb93 (patch) | |
| tree | 306ba784eb755b101d8a7c0b887bb537aa9a63a7 /scripts/switch-timer-api | |
| parent | hw/arm/armsse: Add unimplemented-device stub for CPU local control registers (diff) | |
| download | qemu-5aeb36896600ff92aee1083ed17e80f069befb93.tar.gz qemu-5aeb36896600ff92aee1083ed17e80f069befb93.tar.xz qemu-5aeb36896600ff92aee1083ed17e80f069befb93.zip | |
hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block
The SSE-200 has a CPU_IDENTITY register block, which is a set of
read-only registers. As well as the usual PID/CID registers, there
is a single CPUID register which indicates whether the CPU is CPU 0
or CPU 1. Implement a model of this register block.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions