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| author | Michael Clark | 2018-03-16 20:12:00 +0100 |
|---|---|---|
| committer | Michael Clark | 2018-05-06 00:39:38 +0200 |
| commit | 67185dad16284467dba9b6159f9ec9ec53689582 (patch) | |
| tree | 6ee92a75ea5a597a8a33ffb6dc883679a4a57cf6 /scripts/switch-timer-api | |
| parent | RISC-V: Hardwire satp to 0 for no-mmu case (diff) | |
| download | qemu-67185dad16284467dba9b6159f9ec9ec53689582.tar.gz qemu-67185dad16284467dba9b6159f9ec9ec53689582.tar.xz qemu-67185dad16284467dba9b6159f9ec9ec53689582.zip | |
RISC-V: Clear mtval/stval on exceptions without info
mtval/stval must be set on all exceptions but zero is
a legal value if there is no exception specific info.
Placing the instruction bytes for illegal instruction
exceptions in mtval/stval is an optional feature and
is currently not supported by QEMU RISC-V.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions