diff options
| author | Michael Clark | 2018-04-06 02:46:19 +0200 |
|---|---|---|
| committer | Michael Clark | 2018-05-06 00:39:38 +0200 |
| commit | 6fce529c4b3ecbff17bbd930f6beaac9a6067114 (patch) | |
| tree | 5254f5e326c722b518b78791aec540628ddb95b4 /scripts/switch-timer-api | |
| parent | RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 (diff) | |
| download | qemu-6fce529c4b3ecbff17bbd930f6beaac9a6067114.tar.gz qemu-6fce529c4b3ecbff17bbd930f6beaac9a6067114.tar.xz qemu-6fce529c4b3ecbff17bbd930f6beaac9a6067114.zip | |
RISC-V: Add mcycle/minstret support for -icount auto
Previously the mycycle/minstret CSRs and rdcycle/rdinstret
psuedo instructions would return the time as a proxy for an
increasing instruction counter in the absence of having a
precise instruction count. If QEMU is invoked with -icount,
the mcycle/minstret CSRs and rdcycle/rdinstret psuedo
instructions will return the instruction count.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions