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| author | Jim Wilson | 2019-03-15 11:26:58 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-03-19 13:13:24 +0100 |
| commit | 753e3fe207db08ce0ef0405e8452c3397c9b9308 (patch) | |
| tree | 38d16fb6f1b727dafe750f2e4f638d50f0803132 /scripts/switch-timer-api | |
| parent | RISC-V: Fixes to CSR_* register macros. (diff) | |
| download | qemu-753e3fe207db08ce0ef0405e8452c3397c9b9308.tar.gz qemu-753e3fe207db08ce0ef0405e8452c3397c9b9308.tar.xz qemu-753e3fe207db08ce0ef0405e8452c3397c9b9308.zip | |
RISC-V: Add debug support for accessing CSRs.
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190212230903.9215-1-jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions