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| author | Peter Maydell | 2014-02-26 18:20:01 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-02-26 18:20:01 +0100 |
| commit | 7da845b0f42a791d65045284f90977d636c654cc (patch) | |
| tree | 763ae33ac3ff89bff142de56afd8aeaaaf910480 /scripts/switch-timer-api | |
| parent | target-arm: Fix raw read and write functions on AArch64 registers (diff) | |
| download | qemu-7da845b0f42a791d65045284f90977d636c654cc.tar.gz qemu-7da845b0f42a791d65045284f90977d636c654cc.tar.xz qemu-7da845b0f42a791d65045284f90977d636c654cc.zip | |
target-arm: A64: Make cache ID registers visible to AArch64
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)
visible to AArch64. These are mostly simple 64-bit extensions of the
existing 32 bit system registers and so can share reginfo definitions.
CTR needs to have a split definition, but we can clean up the
temporary user-mode implementation in favour of using the CPU-specified
reset value, and implement the system-mode-required semantics of
restricting its EL0 accessibility if SCTLR.UCT is not set.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions