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| author | Peter Maydell | 2019-02-01 15:55:44 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-01 15:55:44 +0100 |
| commit | 9c72b68ad746a51f63822cffab4d144b5957823a (patch) | |
| tree | 80fed61e3cc2efc83413ddfe5a7a0a308d17fd50 /scripts/switch-timer-api | |
| parent | target/arm/translate-a64: Don't underdecode SIMD ld/st multiple (diff) | |
| download | qemu-9c72b68ad746a51f63822cffab4d144b5957823a.tar.gz qemu-9c72b68ad746a51f63822cffab4d144b5957823a.tar.xz qemu-9c72b68ad746a51f63822cffab4d144b5957823a.zip | |
target/arm/translate-a64: Don't underdecode SIMD ld/st single
In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190125182626.9221-5-peter.maydell@linaro.org
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions