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| author | Bastian Koppelmann | 2014-12-05 15:37:17 +0100 |
|---|---|---|
| committer | Bastian Koppelmann | 2014-12-21 19:35:28 +0100 |
| commit | b5fd8fa34594da327e2965a8c3b5dddf21f862ff (patch) | |
| tree | 723f067ec1b026e82f607a45df08b150c42221a5 /scripts/switch-timer-api | |
| parent | target-tricore: Add instructions of RR opcode format, that have 0x4b as the f... (diff) | |
| download | qemu-b5fd8fa34594da327e2965a8c3b5dddf21f862ff.tar.gz qemu-b5fd8fa34594da327e2965a8c3b5dddf21f862ff.tar.xz qemu-b5fd8fa34594da327e2965a8c3b5dddf21f862ff.zip | |
target-tricore: Add missing 1.6 insn of BOL opcode format
Some of the 1.6 ISA instructions were still missing. So let's add them.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions