diff options
| author | Michael Clark | 2018-03-05 22:33:31 +0100 |
|---|---|---|
| committer | Michael Clark | 2018-05-06 00:39:38 +0200 |
| commit | b8643bd6084be1787a6dc8768a7a1983921fc945 (patch) | |
| tree | 89d854a5e83b6aad4e7656604ccad89a29d169a5 /scripts/switch-timer-api | |
| parent | RISC-V: Make mtvec/stvec ignore vectored traps (diff) | |
| download | qemu-b8643bd6084be1787a6dc8768a7a1983921fc945.tar.gz qemu-b8643bd6084be1787a6dc8768a7a1983921fc945.tar.xz qemu-b8643bd6084be1787a6dc8768a7a1983921fc945.zip | |
RISC-V: No traps on writes to misa,minstret,mcycle
These fields are marked WARL (Write Any Values, Reads
Legal Values) in the RISC-V Privileged Architecture
Specification so instead of raising exceptions,
illegal writes are silently dropped.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions