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| author | Yueh-Ting (eop) Chen | 2022-03-17 08:09:09 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-04-01 00:40:55 +0200 |
| commit | 8ff8ac63298611c8373b294ec936475b1a33f63f (patch) | |
| tree | 9f55127511f489638ec89eb7b97b8d60272861bb /scripts/tracetool.py | |
| parent | target/riscv: Avoid leaking "no translation" TLB entries (diff) | |
| download | qemu-8ff8ac63298611c8373b294ec936475b1a33f63f.tar.gz qemu-8ff8ac63298611c8373b294ec936475b1a33f63f.tar.xz qemu-8ff8ac63298611c8373b294ec936475b1a33f63f.zip | |
target/riscv: rvv: Add missing early exit condition for whole register load/store
According to v-spec (section 7.9):
The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
regardless of current settings in vtype and vl. The usual property that no
elements are written if vstart ≥ vl does not apply to these instructions.
Instead, no elements are written if vstart ≥ evl.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <164762720573.18409.3931931227997483525-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/tracetool.py')
0 files changed, 0 insertions, 0 deletions