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| author | Bin Meng | 2020-06-16 02:50:40 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-06-19 17:25:27 +0200 |
| commit | 49093916d37f663e86316ec54cb77d5515bb973f (patch) | |
| tree | b8bb02546172fbf903ebe552396ce649742e871f /scripts/tracetool/backend | |
| parent | hw/riscv: sifive_u: Support different boot source per MSEL pin state (diff) | |
| download | qemu-49093916d37f663e86316ec54cb77d5515bb973f.tar.gz qemu-49093916d37f663e86316ec54cb77d5515bb973f.tar.xz qemu-49093916d37f663e86316ec54cb77d5515bb973f.zip | |
hw/riscv: sifive_u: Sort the SoC memmap table entries
Move the flash and DRAM to the end of the SoC memmap table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/tracetool/backend')
0 files changed, 0 insertions, 0 deletions