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| author | Bin Meng | 2020-09-03 12:40:14 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | 0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6 (patch) | |
| tree | 2e1a7c7e45eff69893f38bc9cb7448385b5a21b9 /scripts | |
| parent | hw/riscv: Move sifive_u_prci model to hw/misc (diff) | |
| download | qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.tar.gz qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.tar.xz qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.zip | |
hw/riscv: Move sifive_u_otp model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions