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| author | Alistair Francis | 2019-04-20 04:27:02 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:24 +0200 |
| commit | 16fdb8ff64374ed51b246437e13043039a8eb9f9 (patch) | |
| tree | 5afac00fc51a01dbc66daf0f318516126c38d2cb /scripts | |
| parent | target/riscv: Trigger interrupt on MIP update asynchronously (diff) | |
| download | qemu-16fdb8ff64374ed51b246437e13043039a8eb9f9.tar.gz qemu-16fdb8ff64374ed51b246437e13043039a8eb9f9.tar.xz qemu-16fdb8ff64374ed51b246437e13043039a8eb9f9.zip | |
target/riscv: Improve the scause logic
No functional change, just making the code easier to read.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions