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| author | Nathaniel Graff | 2018-12-14 01:19:12 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2018-12-20 21:08:43 +0100 |
| commit | 40061ac0bc5bdfcfa1234dbf8e2a880fd9fc4c2e (patch) | |
| tree | 3c7115f4b802338996e5925858f2fc8d145abe4c /scripts | |
| parent | RISC-V: Enable second UART on sifive_e and sifive_u (diff) | |
| download | qemu-40061ac0bc5bdfcfa1234dbf8e2a880fd9fc4c2e.tar.gz qemu-40061ac0bc5bdfcfa1234dbf8e2a880fd9fc4c2e.tar.xz qemu-40061ac0bc5bdfcfa1234dbf8e2a880fd9fc4c2e.zip | |
sifive_uart: Implement interrupt pending register
The watermark bits are set in the interrupt pending register according
to the configuration of txcnt and rxcnt in the txctrl and rxctrl
registers.
Since the UART TX does not implement a FIFO, the txwm bit is set as long
as the TX watermark level is greater than zero.
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions