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| author | Aleksandar Markovic | 2016-06-10 11:57:36 +0200 |
|---|---|---|
| committer | Leon Alrae | 2016-06-24 14:43:52 +0200 |
| commit | 599bc5e89c46f95f86ccad0d747d041c89a28806 (patch) | |
| tree | ac0fde39e6c036c145a5beba89e3a8b9975e0e50 /scripts | |
| parent | target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D> (diff) | |
| download | qemu-599bc5e89c46f95f86ccad0d747d041c89a28806.tar.gz qemu-599bc5e89c46f95f86ccad0d747d041c89a28806.tar.xz qemu-599bc5e89c46f95f86ccad0d747d041c89a28806.zip | |
target-mips: Implement FCR31's R/W bitmask and related functionalities
This patch implements read and write access rules for Mips floating
point control and status register (FCR31). The change can be divided
into following parts:
- Add fields that will keep FCR31's R/W bitmask in procesor
definitions and processor float_status structure.
- Add appropriate value for FCR31's R/W bitmask for each supported
processor.
- Add function for setting snan_bit_is_one, and integrate it in
appropriate places.
- Modify handling of CTC1 (case 31) instruction to use FCR31's R/W
bitmask.
- Modify handling user mode executables for Mips, in relation to the
bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
reading and writing to FCR31.
- Modify gdb behavior in relation to FCR31.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions